AMD’s new netbook processor, the Bobcat

AMD’s new netbook processor, the Bobcat

AMD shook up their investor meeting today by announcing a new netbook processor, the Bobcat.

Bobcat is an out-of-order processor that can dispatch up to two instructions per cycle from its front-end to the integer and/or floating-point schedulers. Attached to the integer schedulers are four pipelines, two integer pipes and two memory pipes (one load, one store). There is no word on the depth of the integer pipeline as of yet, but I would be shocked if it were less than 12 stages or more than 20.

AMD notes that this core is a synthesizable IP block that’s designed to be mixed and matched with other blocks on an SoC. What this means in English is AMD stores the CPU block in a high-level description language that then gets compiled down into logic gates and laid out on the chip by an automated toolset. The decision to do things this way, vs. the traditional method of customizing a lot of the lower-level design by hand, means trading off performance and some power efficiency for flexibility and time-to-market.

As you can see from the slide, AMD is targeting the sub-1W power envelope with Bobcat, though at launch it will probably hit this target only for the very lowest clockspeed parts; the higher-clocked parts will certainly be above 1W, and possibly up to 2 or 2.5W.

By the time this core launches in 2011 on a 32nm SOI process, Intel will have had Atom on 32nm for a while and will be eyeing 22nm. So, while on a clock-for-clock basis an out-of-order design like Bobcat will certainly smoke the Intel Atom in absolute performance, it’s hard to predict where Intel will have taken Atom in that timeframe.

via Ars

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